With continuous development of semiconductor technology, the development of the semiconductor process node demonstrates a growing trend to fall off the Moore's law. In order to accommodate the decrease of the process node, the channel length in metal-oxide-semiconductor field-effect transistor (MOSFET) has to be reduced. Reducing the channel length may benefit the increase of transistor density on the semiconductor chip and may also be conducive to improving the switching speed of the MOSFET.
However, as the channel length in devices decreases, the distance between the source region and the drain region of the device is also reduced. As such, the controllability of the gate electrode on the channel may be degraded and the gate voltage may not be able to pinch off the channel. As a result, the subthreshold leakage phenomenon, e.g. the short-channel effect (SCE), may easily occur.
Therefore, in order to meet the requirements raised by scaling down the size of the devices, semiconductor technology is gradually shifted away from conventional planar MOSFET to more efficient three-dimension (3D) transistor, such as fin field-effect-transistor (Fin-FET). In a Fin-FET device, the gate may be able to control an ultra-thin structure (e.g. fin structure) from at least two sidewall surfaces of the structure. Therefore, Fin-FET devices may demonstrate much stronger gate-to-channel controllability than planar MOSFETs, and thus may efficiently suppress the SCE. Moreover, compared to some other devices, Fin-FET devices may demonstrate better compatibility with existing manufacturing technology for integrated circuits.
However, the existing Fin-FET devices and fabrication methods may still need to be improved. The disclosed Fin-FET device and the fabrication methods are directed to solve one or more problems set forth above and other problems in the art.